1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, in particular, to a semiconductor device comprising a sense amplifier such as a DRAM (dynamic random access memory), as well as a method of manufacturing the same.
2. Description of the Background Art
Memory Cell Configuration
As example of DRAMs, FIG. 17 shows the configuration of a memory cell part of a one-transistor cell DRAM 90 having one N-channel MOS transistor (NMOS transistor) per memory cell.
In FIG. 17, memory cells MC0, MC1, MC2, and MC3 having NMOS transistors M0, M1, M2, and M3, respectively, are disposed in four portions at which two data lines DL0 and DL1 disposed in parallel and two word lines WL0 and WL1 disposed in parallel cross each other.
A gate electrode and drain electrode of the NMOS transistor M0 are connected to the word line WL0 and data line DL0. A gate electrode and drain electrode of the NMOS transistor M1 are connected to the word line WL0 and data line DL1. A gate electrode and drain electrode of the NMOS transistor M2 are connected to the word line WL1 and data line DL0. The gate electrode and drain electrode of the NMOS transistor M3 are connected to the word line WL1 and data line DL1.
A capacitor CS is connected between each source electrode and each ground potential of the NMOS transistors M0, M1, M2, and M3.
A sense amplifier SA is connected to the data lines DL0 and DL1, respectively. Connections and non-connections of one terminal of the data line DL0 and one terminal of the data line DL1 to a data input-output line IO are controlled by column selection switches CW0 and CW1. The sense amplifier SA has switches SW0 and SW1, the operations of which are controlled by a sense amplifier drive signal.
Connection and non-connection of the other terminal of the data line DL0 and the other terminal of the data line DL1 to a precharge voltage supply line PL are controlled by precharge switches PW0 and PW1. A capacity CD parasitizes the data lines DL0 and DL1.
Operation of the DRAM 90 will next be described by referring to FIG. 17.
Precharge Operation
In a DRAM, a precharge operation is performed prior to the operation of a memory cell. In the precharge operation, the data lines DL0 and DL1 are set to a predetermined precharge voltage VP, and the precharge voltage VP is generally a half of a write voltage VDD (VP=VDD/2).
Power consumption and noise when charging and discharging the data lines can be reduced by setting the precharge voltage VP to an intermediate value between the write voltage VDD to the capacitor and 0 V.
Turning on a precharge clock starts the precharge operation. Turning off the precharge clock results in that the precharge voltage VP is held in a floating state by a parasitic capacity CD of the data line.
Read Operation
Operation of reading the data of a specific memory cell, e.g., a memory cell M0, will be described below.
First, select the word line WL0 to which the memory cell M0 is connected, and apply a pulse voltage (word pulse). Thereby, a signal voltage VS that corresponds to an information voltage (VDD or 0 V) of the capacitor CS in the memory cell M0 is superimposed to the precharge voltage VP, and the resulting voltage is then outputted to the data line DL0, as a positive or negative signal. Note that the operation of outputting the capacitor information to the data line is hereinafter referred to as xe2x80x9cdata calling,xe2x80x9d in some cases. The signal voltage VS can be expressed in the following equation (1).
VS=VDD/2xc2x7CS/CS+CDxe2x80x83xe2x80x83(1)
In general, the capacity of the capacitor CS is far smaller than the parasitic capacity CD. The modem trend in reducing the area of a semiconductor chip is toward smaller memory cell and connection between one data line and more memory cells. Therefore, there has been tendency toward further small capacitor CS and further large parasitic capacity CD.
The signal voltage VS that is a small positive or negative signal is detected and amplified by the sense amplifier SA connected to the data lines DL0 and DL1.
The sense amplifier SA operates by using the precharge voltage VP (VDD/2) as a reference voltage. If the signal voltage VS is greater than VDD/2, the output voltage of the sense amplifier SA becomes VDD. If smaller than VDD/2, it becomes 0.
The amplified voltage corresponding to the information of the capacitor CS is outputted to the exterior by turning on the column selection switches CW0 and CW1, thereby completing the read operation. At this time, information of every non-selected memory cell (hereat, the memory cell M1) on the selected word line (hereat, the word line WL0) is also called by the data line DL1, and the information is amplified by the sense amplifier SA.
When a word pulse is applied, information of every memory cell on the above word line is destroyed. Specifically, since the capacity of the capacitor CS is sufficiently smaller than the parasitic capacity CD, the storage node of the capacitor CS that has been VDD or 0 V is charged to the precharge voltage, irrespective of the information voltage.
More specifically, upon application of the word pulse, the storage node voltage corresponding to a binary information changes from VDD to (VDD/2)+VS, or from 0 V to (VDD/2)xe2x88x92VS. That is, the voltage margin of the binary information of the storage node decreases from VDD to 2VS, resulting in the same as the state that the information is destroyed.
This requires that an individual sense amplifier be placed on all the data lines and, with the sense amplifiers, the signal voltage VS be amplified to VDD or 0 V at the same time, and then rewritten to each memory cell.
Therefore, at the time of the read operation, a sequence of operations such as calling of a small signal voltage VS, amplifying, and rewriting, are performed in parallel with respect to all the memory cells on the selected word line. Only information of a data line, to which the selected memory cell is connected, is outputted to the exterior as a read information.
Write Operation
Write operation to the selected memory cell, e.g., the memory cell M0, is executed by applying a word pulse to the word line WL0 and a binary information voltage (VDD or 0 V) to the data line DL0.
However, as discussed above, the read operation is performed prior to the write operation, because it is necessary to prevent information destroy of the non-selected cell due to the application of the word pulse.
Specifically, the above-mentioned read operation is performed with respect to all the memory cells on the word line WL0, and the amplified voltage corresponding to the information of the memory cell is temporally held on the respective data lines.
Thereafter, the column selection switch CW0 is turned on so that the amplified voltage on the selected data line DL0 is forcedly replaced with a write information voltage from the exterior (the data input-output line IO). This is then inputted to the capacitor CS of the memory cell MC0 that has selected the write information voltage.
At this time, the amplified voltage of all the non-selected data lines (hereat, the data line DL1) on the selected word line (hereat, the word line WL0) is rewritten to the non-selected cell (hereat, the memory cell MC1).
Through the foregoing operations, irrespective of the read or write operation of the selected cell, a sequence of operations such as the calling of the small signal voltage VS, amplifying, and rewriting, is performed in the non-selected memory cell on the selected word line.
In order to output a sufficient signal voltage to a data line, or write the voltage VDD to the capacitor CS, the word pulse voltage is applied as a voltage not less than the sum of the voltage VDD and the threshold voltage Vth of a cell transistor.
Refresh Operation
Refresh operation inherent in DRAMs can be realized by that the foregoing read operation is successively performed with respect to all the word lines.
That is, the refresh operation is performed by word line by word line, and all the memory cells on the word line are refreshed at the same time. Thereby, even if the voltage of the storage node of the capacitor CS in a memory cell is lowered due to current leak and the like, it can be refreshed to the initial value. By performing the above-mentioned refresh operation with respect to all the word lines, the information of all the memory cells are refreshed and thus the stored information of the semiconductor chip is held as a whole.
Overall Configuration of DRAM
FIG. 18 shows the overall configuration of a DRAM. That is, FIG. 18 is a schematic diagram of an exemplary plane configuration of a general DRAM. The memory cell part of the DRAM 90 described by referring to FIG. 17 is contained in a memory array block MAB.
A plurality of memory array blocks MAB are arranged in two columns. In a central part sandwiched therebetween, there is a power supply to form a central power supply CPW.
In the central power supply CPW, there are, for example, pads for connecting and grounding an external power supply, a voltage down converter VDC for lowering an external power supply voltage to an internal power supply voltage, and wiring for transferring the internal power supply voltage and ground voltage. In the memory array block MAB, there are, for example, a plurality of memory cells to form a memory array, as well as peripheral circuits such as a sense amplifier.
FIG. 19 schematically shows the configuration of the memory array block MAB in FIG. 18, in particular, the state that the memory array block MAB is formed by a plurality of memory arrays MA.
FIG. 20 shows the configuration of one memory array MA in the memory array block MAB.
Referring to FIG. 20, the memory cell array is formed by a plurality of memory cells MC spaced at predetermined intervals and in the form of a matrix. The memory cells MC in the direction of the same column are connected to a common bit line BL that is a data line. The bit line BL is connected to a sense amplifier SA. To one sense amplifier, two bit lines BL are connected to form a pair of bit lines.
A plurality of word lines WL are arranged so as to be orthogonal to a plurality of bit lines BL disposed in parallel. These word lines WL are connected in common to the memory cell MC in the direction of the same row.
FIG. 20 shows the memory cell MC as a contour of an active region of the MOS transistor. In FIG. 20, the bit lines BL are connected to source/drain layers of the MOS transistor, and word lines are shown as a gate electrode of the MOS transistor.
The sense amplifier SA uses, as a reference voltage, the voltage of one of two bit lines BL to be connected thereto.
Of the configuration of FIG. 20, the configuration of the surroundings of the sense amplifier SA will be described by referring to FIG. 21.
As shown in FIG. 21, the sense amplifier SA has a P-channel MOS transistor (PMOS transistor) P1 and NMOS transistor N1 connected in series, and a PMOS transistor P2 and NMOS transistor N2 connected in series. Gate electrodes of the PMOS transistor P1 and NMOS transistor N1 are connected in common to connection nodes of the PMOS transistor P2 and NMOS transistor N2. Gate electrodes of the PMOS transistor P2 and NMOS transistor N2 are connected in common to connection nodes of the PMOS transistor P1 and NMOS transistor N1.
Connection nodes of the PMOS transistor P1 and NMOS transistor N1 are connected to a bit line BL. Connection nodes of the PMOS transistor P2 and NMOS transistor N2 are connected to a bit line /BL.
The bit line BL and bit line /BL form one pair of bit lines. Connection and non-connection of the bit lines BL and /BL to data input-output lines IO and /IO are controlled by an NMOS transistor MSW that is controlled by a signal of a column selection line CSL.
Power supply wirings WR1 and WR2, and sense enable wirings SEp and SEn are disposed so as to be orthogonal to plural pairs of bit lines.
The power supply wiring WR1 is a wiring to which an internal voltage VDD is supplied, and is paired with the sense enable wiring SEp. Both are electrically connected with each other through a PMOS transistor MP1 that is a driver transistor.
The power supply wiring WR2 is a wiring to which a ground voltage GND is supplied, and is paired with the sense enable wiring SEn. Both are electrically connected with each other through an NMOS transistor MN1 that is a driver transistor.
Source electrodes of PMOS transistors P1 and P2 forming the sense amplifier SA are connected to the sense enable wiring SEp. Source electrodes of NMOS transistors N1 and N2 are connected to the sense enable wiring SEn.
In the foregoing configuration, every time sense amplifier drive signals /SAE and SAE are applied to the PMOS transistor MP1 and NMOS transistor MN1, the internal voltage VDD and ground voltage GND are applied to the source electrodes of the PMOS transistors P1 and P2 forming the sense amplifier SA, and to the source electrodes of the NMOS transistors N1 and N2. For the rest, these source electrodes are in the state of floating. This operation aims at lowering a standby current of the sense amplifier SA.
FIG. 22 is a schematic diagram of wiring for power supply to sense amplifiers SA on memory arrays MA.
As described with respect to FIG. 21, to the sense amplifiers SA, there are supplied the internal voltage VDD through the power supply wiring WR1 and sense enable wiring SEp, and the ground voltage GND through the power supply wiring WR2 and sense enable wiring SEn. As shown in FIG. 22, the voltages of the power supply wirings WR1 and WR2 are fixed through mesh power lines MPL1 and MPL2 that are connected to the central power supply CPW.
A plurality of power supply wirings are connected to an individual mesh power line. That is, the mesh power line MPL1 is a wiring for supplying the internal voltage VDD and is connected to the power supply wiring WR1 disposed in each memory array MA. The mesh power line MPL2 is a wiring for supplying the ground voltage GND and is connected to the power supply wiring WR2 disposed in each memory array MA.
A plurality of the mesh power lines MPL1 and MPL2 are arranged alternately. These mesh power lines MPL1 are connected to an output line OL1 of a voltage down converter VDC for pulling down an external power supply voltage Vdd to the internal voltage VDD. An external power supply voltage Vdd is fed from the exterior of the semiconductor chip through an external voltage pad PD2.
The plural mesh power lines MPL2 are connected to a ground line OL2 that is connected to a ground pad PD1.
Reference is now made to a timing chart in FIG. 23, and problems involved in reading data from a memory cell will be described by referring to FIG. 21.
FIG. 23 illustrates voltage fluctuations in the sense enable wirings SEp and SEn, and in the bit lines BL and /BL. Waveforms indicated by solid lines represent phenomena that are the problems, and waveforms indicated by broken lines represent ideal waveforms.
When applying the sense amplifier drive signals SAE and /SAE at the timing indicated by arrows in FIG. 23, the internal voltage VDD is supplied through the sense enable wiring SEp to the source electrodes of the PMOS transistors P1 and P2 forming the sense amplifier SA. And, the ground voltage GND is supplied through the sense enable wiring SEn to the source electrodes of the NMOS transistors N1 and N2.
At this time, ideally, the bit line BL rises sharply as shown by the broken line at the timing of receiving the sense amplifier signal SAE, and the bit line BL falls sharply at the time of receiving the sense amplifier drive signal /SAE.
However, when the plural sense amplifiers SA are turned on at the same time, as shown in FIG. 23, the potentials of the sense enable wirings SEp and SEn fluctuate by the amount of xcex94VDD and xcex94GND, respectively.
The reason for this is as follows. Since the plural sense amplifiers are connected to the sense enable wirings SEp and SEn, the wiring length is long and wiring capacity is large. Therefore, a voltage drop due to the wiring capacity is produced on the sense enable wiring SEp, and a voltage buildup is produced on the sense enable wiring SEn. Electronic current and hole current contributing to voltage fluctuations have the same time integral value according to conservation of charge.
Hence, fluctuations in the internal voltage VDD and ground voltage GND for driving the sense amplifiers degradates the drive capability of the transistors forming the sense amplifiers. This elongates a delay time tRCD between reading when a word pulse is applied to a word line and sensing and discrimination of the information of a bit line. As a result, there is the problem that the sense operations of the sense amplifiers become dull.
It is an object of the present invention to provide a semiconductor device capable of avoiding that the sense speed of each sense amplifier lowers due to drives of a plurality of sense amplifiers.
A semiconductor device according to a first aspect of the invention includes the following components of (i) to (v). Specifically, (i) is a main semiconductor layer of a first conductivity type being disposed entirely on a main surface of a semiconductor substrate and having above it plural wiring layers; (ii) is a first semiconductor layer of the first conductivity type selectively disposed in a first main surface of the main semiconductor layer; (iii) is a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type that are selectively disposed in the first main surface of the main semiconductor layer and are adjacent to the first semiconductor layer so as to sandwich therebetween the first semiconductor layer; (iv) is a fourth semiconductor layer of the second conductivity type selectively disposed in an inner part of the main semiconductor layer beneath the first semiconductor layer so that it makes contact with at least a bottom surface of the first semiconductor layer; and (v) is a fifth semiconductor layer of the first conductivity type disposed in a second main surface of the main semiconductor layer. The fifth semiconductor layer is disposed in such a thickness as to form a PN junction with the fourth semiconductor layer and has a junction capacitance between the fourth and fifth semiconductor layers. The plural wiring layers have a first power supply wiring to which a first voltage is supplied and a second power supply wiring to which a second voltage lower than the first voltage is supplied. The third semiconductor layer is electrically connected to the first power supply wiring, and the second semiconductor layer is electrically connected to the second power supply wiring.
The fifth semiconductor layer of the first conductivity type disposed entirely in a depth from the second main surface of the main semiconductor layer is located at such a thickness as to form a PN junction with the fourth semiconductor layer. Therefore, a junction capacitance is present between the fourth and fifth semiconductor layers. When a voltage drop due to the parasitic capacity is produced on the first power supply wiring, charge can be supplied from the junction capacitance to the first power supply wiring through the third and fourth semiconductor layers. As a result, the voltage of the first power supply wiring is maintained at a fixed value. In addition, by making the fifth semiconductor layer have such a thickness as to form a PN junction with the fourth semiconductor layer, the distance between the fifth and second semiconductor layers can be reduced to lower the resistance value of the second semiconductor layer. When a voltage buildup due to the parasitic capacity is produced an the second power supply wiring, it is easy to reduce charge from the second power supply wiring through the second semiconductor layer. As a result, the voltage of the second power supply wiring is maintained at a fixed value.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.